Mohammad Reza Zeinali - Advancom Lab, School of Electrical and Computer Engineering, College of Engineering University of Tehran Tehran, Iran
Samad Sheikhaei - Advancom Lab, School of Electrical and Computer Engineering, College of Engineering University of Tehran Tehran, Iran

A 1.8-V second-order discrete-time single bit delta-sigma modulator over a signal bandwidth of 2 kHz is presented in this paper. In order to reduce the voltage swings of the integrators, the feed forward topology is selected. In addition, a single-stage fully-differential class AB folded-cascode operational transconductance amplifier (OTA) for low-voltage and fast-settling switched-capacitor circuits is used. Also, a dynamic comparator is employed to save power consumption. The modulator is designed and simulated in 180-nm CMOS technology and achieves 102 dB peak signal-to-noise-and-distortion-ratio (SNDR) that is equal to 16.7 bit ENOB and 177.9 dB FOM, which is among the best reported FOMs for delta-sigma modulators. The core area of the chip is 300μm*350μm and the total power consumption is 51μW.

Delta-sigma modulator, Low power, High FOM.