A Novel Low-Power FPGA-based 1-1 MASH ΔΣ Time-to-Digital Converter Employing one Counter for both Stages
عنوان مقاله: A Novel Low-Power FPGA-based 1-1 MASH ΔΣ Time-to-Digital Converter Employing one Counter for both Stages
شناسه ملی مقاله: JR_JECEI-7-2_005
منتشر شده در در سال 1398
شناسه ملی مقاله: JR_JECEI-7-2_005
منتشر شده در در سال 1398
مشخصات نویسندگان مقاله:
- - - Department of Electrical Engineering, Mahshahr Branch, Islamic Azad University, Mahshahr, Iran.
- - - Department of Electrical Engineering, Mahshahr Branch, Islamic Azad University, Mahshahr, Iran.|Department of Electrical Engineering, Faculty of Engineering, Shahid Chamran University of Ahvaz, Ahvaz, Iran.
- - - Department of Electrical Engineering, Mahshahr Branch, Islamic Azad University, Mahshahr, Iran.|Department of Electrical Engineering, Faculty of Engineering, Shahid Chamran University of Ahvaz, Ahvaz, Iran.
خلاصه مقاله:
- - - Department of Electrical Engineering, Mahshahr Branch, Islamic Azad University, Mahshahr, Iran.
- - - Department of Electrical Engineering, Mahshahr Branch, Islamic Azad University, Mahshahr, Iran.|Department of Electrical Engineering, Faculty of Engineering, Shahid Chamran University of Ahvaz, Ahvaz, Iran.
- - - Department of Electrical Engineering, Mahshahr Branch, Islamic Azad University, Mahshahr, Iran.|Department of Electrical Engineering, Faculty of Engineering, Shahid Chamran University of Ahvaz, Ahvaz, Iran.
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کلمات کلیدی: Delta-sigma modulation, Gated Switched-Ring Oscillator (GSRO), Multi-stage-noise-shaping (MASH), Oversampling, Voltage-Controlled Oscillator (VCO)
صفحه اختصاصی مقاله و دریافت فایل کامل: https://civilica.com/doc/1124619/