Amir Baghi Rahin - Department of Electrical Engineering, Sardroud Branch, Islamic Azad University, Tabriz, Iran
Afshin Kadivarian - Department of Electrical Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran
Vahid Baghi Rahim - Department of Electrical Engineering, Sardroud Branch, Islamic Azad University, Tabriz, Iran

Designing smaller area, low power consumption, low PDP and high speed full adder is always in demand. There are growing requests for low-power and high speed full adders in several applications of computing systems such as computer graphics, scientific computing and image processing. As the channel length tends to the nanoscale regime, the use of MOSFET as a basic device in the full adder achieves its functional limitations such as average power dissipation and speed. In this paper, a ۱-bit full adder cell is proposed using a CNTFET transistor with a supply voltage of ۰.۵V for mobile applications. Using HSPICE software, all the main full adder parameters such as leakage power, average power consumption, delay and power delay product (PDP) were measured. In this study, leakage power of ۳۳.۵pW, delay of ۱۲۳.۷۱ps, average power consumption of ۹۳nW and PDP of ۱۱.۵۱×۱۰-۲۱ J were obtained.

Full adder (FA); Ultra low-power; PDP (power-delay product); CNTFET transistor; Mobile applications