Amir Baghi Rahin - Department of Electrical Engineering,Sardroud Branch, IAUTTabriz, Iran
Afshin Kadivarian - Department of Electrical Engineering,Science and Research Branch, IAUTTehran, Iran
Saba Naseri Akbar - Department of Electrical Engineering,Islamshahr Branch, IAUT,Tehran, Iran
Vahid Baghi Rahin - Department of Electrical Engineering,Sardroud Branch, IAUT,Tabriz, Iran

In this paper, an optimized design of dynamiclogic using FinFET transistors for one-bit full adder cell ispresented. The proposed full adder was simulated in ۳۲ nmtechnology by considering various conditions in terms of supplyvoltage, capacitive loads and temperature changes. Based on theobtained results, it was determined that the proposed full adderis faster compared to other full adders and has a low powerdelay product (PDP) than the compared structures. Theproposed full adder can still work well at ۰.۳V supply voltage.Based on the simulation results, at the supply voltage of ۰.۳ Vand the load capacitors from ۱.۴ to ۹.۴ fF, the propagation delayis in the range of ۱۵۱.۷۵ to ۲۴۸.۲۵ ps, the average powerconsumption is in the range of ۸۹.۹۵ to ۲۳۸.۸۰ nW, and the PDPvaries from ۱۳.۶۵ to ۵۹.۲۸ aJ. The amount of leakage power inthis operating voltage is equal to ۵.۶۳ nW. The values obtainedat the supply voltage of ۰.۳ V indicate the excellent performanceof the proposed ۱۶-transistor dynamic full adder, which makesit a candidate for high-speed low-voltage applications

dynamic logic, full adder (FA), FinFETtransistor, high-speed, low-voltage.