sattar samadigorji - babol nushirvani university of technology department of electrical engineering- babol -iran
bijan zakeri - babol nushirvani university of technology department of electrical engineering- babol -iran
mohammad reza zahabi - babol nushirvani university of technology department of electrical engineering- babol -iran

the aim of this paper is to minimize output phases nois for the pure signal synthesis in frequency synthesizers.for this purpose frist an axact mathematical model of phase locked loop based frequency synthesizer is described and analyzed.then an exact closed-from formular in terms of synthesizer bandwidth and total output phasee noise is extracted.based on this formula the phase noise diagram as a function of bandwidth is plotted.from the analysis and simulation results it is observed taht the synthesizer has a minimum phase noise at a particular bandwidth.

frequency synthesizers-phases noise-phases-locked loop-phases noise reduction