Ebrahim Pakniyat - Department of Electronic Engineering, Imam Reza International University
Seyed Reza Talebiyan - Department of Electronic Engineering, Imam Reza International University
Famaz Loghmani - Department of Electronic Engineering, Imam Reza International University

This paper presents a new structure of 1-bit full adder for sub-threshold technology. It compares full adder sub-circuits and also compares the proposed full adder with common full adders in terms of propagation delay, power consumption, power delay product and square power delay product in sub-threshold technology. HSPICE simulations show that the power dissipation, power delay product and square power delay product of the proposed 16T full adder is 5%, 16% and 20% better than the best common full adder TG, respectively. The full adder circuits are compared in 260 (mV) supply voltage.

1-bit full adder, sub-threshold voltage technology, propagation delay, power consumption