Majid Jafari - Department of Computer, South Tehran Branch, University of Islamic Azad, Iran Received
Ali Broumandnia - Department of Computer, South Tehran Branch, University of Islamic Azad, Iran
Navid Habibi - Department of Computer, South Tehran Branch, University of Islamic Azad, Iran
Shahab Forgani - Department of Computer, South Tehran Branch, University of Islamic Azad, Iran

One the challenging in hardware performance is to designing a high speed calculating unit. The higher of calculations speeds in a computer system will be pointed out in terms of performance. As a result, designing a high speed calculating unit is of utmost importance. In this paper, we start design whit this knowledge that one multiplier made of several adder and one divider made of several sub tractor. Therefore, if the fast adder or fast multiplier designed, performance will be improved. In this design, a circuit is designed in a manner that without a need for transforming numbers or letters from the given bases into binary bases, the multiplication of two numbers for the same base is done in that base. Reduction in the number of conversions in the calculating unit, causes reduction in the consumption power and an increase in the operating speed of the system. In this design, a very small Data Oriented Memory is used to save numerical and character data.

Data Oriented Memory; same base multiplication; Content Addressable Memory; Sub tractor; Category