An Experiment On Designing Asynchronous 4-Bit Up Counter Using JK Flip-Flop And Implementing Using Seven-Segment LED Display

Asynchronous counters are widely used as frequency dividers and are preferred for low power applications and where low noise emission is needed. In this paper, we present a way of designing a 4-bit asynchronous up counter. This circuit contains four jk flip-flops, a BCD-To-Seven segment converter, and a seven-segment LED display. Results of simulation are presented as well as experimental data. The output of the counter circuit is tested using a multimeter and a seven-segment display, for which a converter device is needed. After experimenting on the asynchronous counters, we concluded that these types of counters are easy to construct because of the low number of ICs in the circuit, which will also lower the total price of designing such a circuit. However, there are some disadvantages to asynchronous counters and in the center of those, is the propagation delay. The external clock pulse signal is only given to the first flip flop, and the output of each flip flop will be the clock input of the next one. This way, every output will take its time unlike the synchronous counters, in which all flip flops have a common clock, and the outputs are available at the same time.