A novel comprehensive comparative study of pulse triggered flip-flops in deeply submicron technology

Flip-flops are the main factor in the power dissipation of clock network, which includes about 50% of the total system power consumption. In fact, flip-flops affect the clock frequency because their delay accounts for a significant portion of the clock cycle. Flip-flops are also an essential unit in the design of digital circuits Therefore, having a low power and high speed flip-flops is equivalent to creating an optimal digital system. Accordingly, in this paper, a new comparative study of pulse triggered flip-flops in submicron technology is presented. Four new pulse triggered flip-flops and two conventional types are completely compared with each other and also with conventional TGFF flip-flops in terms of power consumption, delay and power-delay-product. The effect of technology scaling on these parameters was better investigated by simulating flip-flop circuits in both 90 and 45 nm CMOS technologies. Among all circuits, the flip-flop with IP architecture (The most optimal circuit) recorded a 52% reduction in dynamic power consumption compared to TGFF; also, this flip-flop has reduced the input-to-output and clock-to-output delay by 97% and 25%, respectively and 98% of the PDP parameter compared to the TGPL and CPFF flip-flops.