Analysis and Design of High Performance Master-Slave Flip-flop for Deep sub-micron Technology

Power consumption not only at the system level, but also at the circuit level is one of the most important concerns of electronic designers. Delay and the chip area is one of the parameters involved in optimizing the circuit. Flip-flops are one of the widely used devices in the field of digital electronics. Therefore, In this paper, a High Performance Master-Slave flip-flop is designed for deep sub-micron technology and complete study was performed in terms of power consumption, delay, PDP parameter and area. The simulations were performed by Hspice software at ۹۰ and ۴۵ nm CMOS. Compared to TGFF flip-flops, proposed flip-flops had an ۸۳% reduction in the average leakage power consumption parameter and ۹۲.۶% reduction in average dynamic power consumption at ۴۵ nm. In the power-delay product (PDPD-Q) parameter as well as the PDPclk-Q, the proposed flip-flop recorded a ۹۳% and ۹۴% decrease, respectively and Also, HPFF and proposed flip-flops had a ۵۰% and ۴۱% reduction in area, respectively compared to the TGFF flip-flop. The results in ۴۵nm technology show that the proposed flip-flop is better in many parameters than other master-slave flip-flops