Δ∑ Fractional-N Synthesizer for GSM-E-۹۰۰ Frequency Standard

This paper presents an integrated phase-locked loop (PLL) frequency synthesizer for wireless communication application in standard ۰.۱۸ µm CMOS process. Delta sigma modulator used for reducing phase noise. The use of  modulation concepts results in a beneficial noise shaping of the phase noise (jitter) introduced by fractional-N division. The this technique has the potential to provide low phase noise, fast settling time, and reduced impact of spurious frequencies when compared with existing fractionalPLL techniques. Simulation results show that the phase noise of frequency synthesizer is -۱۰۸ @۱MHz offset, and the PLL synthesizer provides output frequencies ۸۸۰-۹۱۵ MHz in uplink and ۹۲۵-۹۶۰ MHz in downlink. Fref is ۲۶ MHz and channel spicing is ۷۰۰ KHz. Moreover, benefiting from the combination of current-mode-logic (CML) the PLL consumes a total power dissipation of only ۲۴.۳۵ mW with a single ۱.۸ V supply including all the buffers. Although prescaler increases settling time (ts), it decreases power consumptions. Settling time in uplink is ۴۲۵ ns and in downlink about ۴۷۵ ns.