Improving table control speed on the OpenFlow switch on the FPGA platform using the pipeline structure

In this paper, the design, synthesis and, simulation of the controlling block table is done on the FPGA's processing chip. The design of the controlling block current tables will be based on decreasing delays and improving the efficiency for the optimization ,furthermore improving the switch performance is the innovation of this research. In order to achieve this goal, the results of simulation and synthesis have been compared with several similar researches carried out in this regard. the new proposed architecture, combining the two methods of pipeline andMemory parallelization are presented and the simulation results and implementation are obtained as well. According to the results obtained from the proposed structure that is designed as a pipeline, the flow search rate can reach ۴۰۰ MilionLookup / second that shows a significant improvement compared to other researches all around the world.