Simulation and Analysis of Delay for a Novel Latch Dynamic Comparator in ۱۸۰nm technology for biomedical applications

In today’s modern world, the demand for fast, low power, and high-resolution analog-to-digital converters (ADC) is more than any time in the past. Comparators are one of the four main parts of an ADC. In this paper, a fast comparator enjoying low power consumption and high resolution which would be beneficial in biomedical applications, is proposed. To increase the speed of the circuit, a latch structure is employed at input stage; this results in a reduction in delay and, as a result, an increase in the speed of the circuit. An analysis of delay of dynamic latch comparator is presented as well. Simulation is done in ۱۸۰ nm technology at a frequency of ۰.۵GHz r; for ۱۸۰nm technology and ۰.۵GHz operation frequency, the delay and the power consumption are found to be ۳۷۴ ps and ۱۰۵ μW, respectively