Design and Analysis of Hetero Dielectric Dual Material Gate Underlap Spacer Tunnel Field Effect Transistor

This paper presents a design and analysis of a Hetero Dielectric Dual Material Gate Underlap Spacer Tunnel Field Effect Transistor, aiming to enhance device performance and overcome inherent limitations. The proposed design incorporates a hetero dielectric gate stack, which consists of two distinct dielectric materials such as high-k-dielectric material as hafnium oxide (HfO۲) and low-k dielectric material as silicon dioxide (SiO۲). With different permittivity values. By selecting these materials, the gate stack can effectively modulate the electric field distribution within the device, improving electrostatic control and reducing ambipolar conduction. Furthermore, an underlap spacer is introduced in the presented structure to create a physical separation between the source and the channel regions. This spacer helps in reducing the direct source-to-drain tunneling current, enhancing the Ion/Ioff current ratio and reducing the subthreshold swing. Additionally, the underlap spacer enables improved gate control over the tunneling process. The proposed Tunnel Field Effect Transistor design is thoroughly analyzed using numerical simulations based on the technology computer-aided design (TCAD) simulator. Performance metrics as the on-state current (Ion), the off-state current (Ioff), ION/IOFF ratio, drain conductance (Gd) and transconductance (Gm) to assess the device's performance. Therefore, these improvements contribute to lower power consumption and improved circuit performance, making it a promising device for low-power applications.