VCO Design and Simulation Using TSMC ۰.۱۸ m Process to Meet IEEE۸۰۲.۱۱a Requirements

A complimentary topology is used incorporating TSMC ۰.۱۸ mm process to design a CMOS VCO with the center frequency of ۵.۴ GHz. Simulation results showed tuning range of ۱۳%. The phase noise at ۱ MHz offset was measured to be -۱۱۸.۷ dBc/Hz. The VCO core power consumption was ۳.۳ mW when the power supply voltage was set to ۱.۵ V. Simulation results verified that the designed structure meets the IEEE۸۰۲.۱۱a requirements.