Design of a Novel Sigma-Delta modulation with reduced elements and phase noise reduction utilizing a MOS-Transistor as a phase shift component

The frequency delta-sigma modulator (FDSM), which uses a variable frequency oscillator, is a unique substitute for traditional delta-sigma modulators. This is beneficial for sensor applications since an ADC may be inherently integrated with the sensors. The noise floor, on the other hand, dramatically reduced the signal-to-noise ratio in FDSMs. It is shown that reducing the phase noise of the oscillator may significantly lower the noise floor. In this study, an unique sigma delta with decreased components is suggested, as well as a phase noise reduction network, to lower the phase noise of an FDSM oscillator based on the self-injection locking principle. The core oscillator is built in CMOS ۱۸۰ nm and has a free-running frequency of ۳۳ GHz with a tuning range of up to ۵.۵ GHz. Once the noise shaping functionality of the transistor is fulfilled, a portion of the oscillator output current is grabbed and injected into the oscillator through a MOS transistor. Then, an analytical technique is used to explain how phase noise in such self-injection locked oscillators decreases. The influence of substrate coupling noise on oscillator phase-noise is also explored. The theoretical tools are extended to investigate the effect of a phase noise reduction network on extra phase noise caused by substrate noise coupling. Finally, simulation results are depicted in accordance with theory. The suggested approach reduces core oscillator phase noise by ۶ dB at ۱۰ KHz and ۳.۵ dB at ۱ MHz offset frequency