Optimal design of low noise and low power CMOS Low Noise Amplifier

The main purpose of this paper isa Low Noise Amplifier for UWB Radio Receiver at 8.72GHzusing 0.18ƒتm CMOS Technology.UWB Radio Receiver which made up between the frequency range of 3.1GHz to 10.6GHz.The basic architecture of LNA comprises a RF amplifier in the middle of input matching network and the output matching network. We have designed a low noise amplifier that consist low noise figure, good input and output impedancematching and high gain and stability that exhibits the properties of standard MAX -2640 LNA, where operating temperature is 27 oC gain is 20dB and would have good stability. We used cadence tool for the best performance and accuracy for results, this work represents an LNA schematic compose of Common gate LNA and Cascode LNA, where Common gate LNA is used for excellent input and output matching and the cascode LNA for low Noise figure and high gain, an additional feature is that single ended LNA employs inductive source degeneration concept (inductor Ls is connected to the source of transistor M1) where M1has a greater control over the value of the real part of the input impedance through the choice of the inductance. Cascode transistor M2 is used to reduce the interaction of the tunedoutput with the tuned input and M2is used to reduce the interaction of the tuned output with the tuned input.