A fault-tolerant routing algorithm in 3D topology manycore processors

The unprecedented progress in semiconductor technology has provided great opportunities for commercialized computationally intensive applications. Amdahl's law wasapplied for multiprocessor computers till several years ago but his laws are now useful to help us understand and develop usingmanycore chip multiprocessors (CMP). Obviously manycorebased designs could not be done blindfold and it needs detailedcalculations. In CMP’s with hundred processing cores, 3Dtopology in the form of network-on-chip (NoC) can be used for shortening the wires length leads to low latency, low powerdissipation and scalability. Meanwhile faults can occur in NoC both at the router and in communicational links. There are manyfault-tolerant solutions that their function is based on rerouting the packets. In this paper we propose a fault-tolerant techniquewhich is completely adaptive and use available non-broken links. The focus of this technique is keeping the performance of NoCwhen there is a faulty link and the packets from a source to adestination never get lost. Experimental results shows that this algorithm can tolerate more than 10 faulty links in different parts of NoC and it can achieve more than 97% reliability.