Design of an ASIP processor for Rendering Algorithms

The main purpose of this article is to design an ASIP processor for heavy and time-consuming process of rendering algorithms. Give the importance of speed and flexibility in image processing applications, ASIP processor is designed for rendering algorithms called ASIP_1. In ASIP_1 the time of execution of rendering algorithms is 3.06 microsecond. Then it is optimized from the software and hardware points of views.By hardware optimization in ASIP_2 the time of execution of rendering algorithms decreased to 1.10 microsecond in comparison to initial proposed ASIP_1. Using software to implement hardware of the rendering algorithms in ASIP_3 processor increases the cost of programming. However, it totally reduces the number of consuming gates.