Analysis and Design of the High Efficiency Binary Comparator

The binary comparator is the one of the most important of the arithmetic unit in the digital processing systems. This paper presents time delay analysis and design of the high efficiency binary comparator. And also based on this analysis, different structure of 8-bit comparators are designed and proposed. The structures are 4-4, 5-3 and 3-3-2 using for implementation of 8-bit comparator. Simulation result verifies that 3-3 -2 architecture for implementing of 8-bit comparator increases performance of comparator by 22%. The proposed comparators are simulated with 180 nanometer CMOS technology in the Cadence and power supply of comparators is 1.8 Volt.