FinFET-based Full Adder using SDTSPC Logic with High Performance
سال انتشار: 1399
نوع سند: مقاله ژورنالی
زبان: انگلیسی
مشاهده: 415
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شناسه ملی سند علمی:
JR_IJMEC-10-38_005
تاریخ نمایه سازی: 25 تیر 1400
چکیده مقاله:
This paper presents an optimized design of SDTSPC logic (stacked diode transistor based TSPC) using FinFET transistors for ۱-bit full adder. The analysis was performed for average power consumption, leakage power, propagation delay and power delay product (PDP) for different supply voltages, loads and temperatures. Comparing the proposed FinFET-based full adder design with MOSFET-based SDTSPC full adder, we achieved a ۹۵.۷۵% improvement in leakage power consumption. The proposed scheme is also compared with several previous designs and based on different simulations, the proposed FinFET-based full adder exhibits excellent performance. The proposed high-efficiency full adder cell operates at low voltages (۰.۴ V) even with large capacitors.
کلیدواژه ها:
SDTSPC (stacked diode transistor based TSPC) logic ، FinFET transistor ، power delay product (PDP) ، TSPC logic
نویسندگان
Amir Baghi Rahin
Department of Electrical Engineering, Sardroud Branch, Islamic Azad University Sardroud, Iran
Vahid Baghi Rahin
Department of Electrical Engineering, Sardroud Branch, Islamic Azad University Sardroud, Iran