VHDL Based Symbolic Model Checker with Improved CTL Property Language

Most existing verification tools suffer from having a standard language for design specification. Although most of these tools support standard hardware description languages, but the subset of the HDL they support is very limited. In this paper we introduce a verification tool, which does not have these limitations. We use symbolic model checking to verify a VHDL design. A Data Flow Graph (DFG) is extracted from the VHDL code, which has been fully implemented in object oriented format in C++ and covers about 90% of the synthesizable subset of VHDL. We use Reduced Ordered Binary D ecision Diagrams to represent FSM description of a system in terms of transition relations. The conversion of DFG to BDDs is done inside the DFG classes. For the property language, we have used CTL with extensions to include event sequence structures and word-level properties. For these extensions, we have implemented a Multi-valued Decision Diagram (MDD) package over an existing BDD package. The complete package is put into a user-friendly environment for automatic verification of FSMs. We have compared our results with VIS and SMV tools.