Optimization of Logic Circuits at Gate Level Using Genetic Algorithms with Early Stopping

Gate-level evolutionary design is an artificial evolution based promising path to design of logic circuits. A practical disadvantage of evolutionary algorithms like genetic algorithm is longer running time. One way to reduce the calculation time in each generation is to stop evaluations early if they hold little promise of attaining high fitness. However, there is a probability of prematurely stopping evaluation of a phenotype which may have useful genes to produce better offspring. In this paper, we applied both basic genetic algorithm and early stopping genetic algorithm as an optimized approach to produce logic circuits from different truth tables. For this purpose we used three truth tables to evaluate the effectiveness of proposed genetic algorithm. The experimental results reveal that the number of generations has considerably been decreased so the run time has been reduced significantly. This is because of giving another chance to these individuals to generate individuals with better fitness.